The present invention related to integrated circuits. More particularly the invention relates to an integrated circuit having improved substrate capacitance isolation at input nodes of the integrated circuit.
Integrated circuits, IC, are generally formed on an insulative substrate, such as silicon, gallium arsenide, or the like. The bottom surface of the substrate has a metal layer deposited on it by vapor deposition. The opposite surface has active and passive circuitry, such as transistors, diodes, resistors and capacitors, formed on it using well known IC processing techniques. Alternating layers of silicon dioxide and metal are deposited over the active circuitry and are etched to form bonding pads, trace runs and interconnects. The IC, containing the electrical circuitry, is placed in a package device or upon a substrate having leads, legs, or runs extending therefrom for electrically connecting the IC to external electrical circuitry. Electrical connections between bonding pads on the IC and the legs of the package device or the runs on the substrate are made via wire bonds.
Parasitic or substrate capacitance exists between the metal layers on the opposing surfaces of the substrate. Generally this capacitance is in the range of 0.15 picofarads. When in the presence of A. C. grounds, this capacitance has the effect of reducing the impedance of an input amplifier on the IC. The bottom metal layer of IC's are connected to A. C. ground, which is generally set at the lowest electrical potential applied to the device. For example, if the IC has applied electrical potentials of .+-.5 volts and .+-.15 volts, the metal layer is connected to the -15 volts. For a high impedance amplifier IC being used as an active probe or an input amplifier in a test instrument, such as an oscilloscope, logic analyzer, or the like, it is important to keep A. C. grounds away from the first input stage to reduce the input capacitance as much as possible. This is especially true if the amplifier input is being driven by a voltage divider attenuator circuit. Besides the parasitic capacitance there is also distributed resistance in the substrate that is effectively in series with the substrate capacitance. This series capacitive/resistive network is in parallel with the lower leg of the attenuator. The upper leg of the attenuator requires corresponding compensation to offset the parasitic capacitance and distributed series resistance developed in the IC. It is very difficult to compensate the upper leg for this distributed series resistance. Once an electrical signal enters the amplifier and is behind the first stage, the impedance is much lower and the substrate capacitive/resistive network and A. C. grounds are less critical.
U.S. Pat. No. 4,646,002 to Tuszyski describes a bootstrapping scheme for driving the bottom metal surface of the substrate with the output of the IC circuitry to reduce base-to-substrate capacitance. The device is characterized as a high impedance buffer circuit for use in a high impedance broad band probe. The circuit is formed on an the IC substrate having a metal layer on the bottom surface. The IC substrate is supported by a second substrate having its own metal layer. The metal layer of the IC substrate is driven by the output of the circuitry on the IC device. The metal layer on the supporting substrate is connected to A.C. ground. The intent of this design is to reduce the base-to-substrate capacitance of the transistor formed on the original substrate. However, there are drawbacks to this type of design. The geometry of the bottom metal layer covers the complete surface of the substrate requiring the buffer circuit to drive the total substrate capacitance of the IC. In addition, the further the metallized layer is from the active devices the more difficult it is to design an amplifier for driving the substrate at high frequencies. Additionally, it would be difficult to control feedback to areas not needing capacitive isolation.
What is needed is an improved IC design for isolating substrate capacitance in integrated circuit devices that overcomes the short comings of previous designs. The IC can be used as a high impedance input to an ultra low capacitance test probe or an input stage to electrical test equipment.